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Lateral P-N Junction Control by Silicon Recoil Implantation

IP.com Disclosure Number: IPCOM000035981D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Baratte, H: AUTHOR [+2]

Abstract

One major problem in fabricating submicron semiconductor devices by ion implantation is the inevitable lateral straggle of the implant under a mask edge and the further extension upon subsequent annealing that is required for activation of the implanted species. The diffusion problem is severe for all commonly used p-type dopants in GaAs (Be,Mg,Zn...) and becomes worse for implantations conducted at high doses. The diffusion is accentuated in (Al,Ga)As compared to GaAs, which poses problems for fabrication of Heterostructure Field-Effect Transistor (HFET)- and Heterostructure Bipolar Transistor (HBT)-based integrated circuits.

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Lateral P-N Junction Control by Silicon Recoil Implantation

One major problem in fabricating submicron semiconductor devices by ion implantation is the inevitable lateral straggle of the implant under a mask edge and the further extension upon subsequent annealing that is required for activation of the implanted species. The diffusion problem is severe for all commonly used p-type dopants in GaAs (Be,Mg,Zn...) and becomes worse for implantations conducted at high doses. The diffusion is accentuated in (Al,Ga)As compared to GaAs, which poses problems for fabrication of Heterostructure Field-Effect Transistor (HFET)- and Heterostructure Bipolar Transistor (HBT)- based integrated circuits. A dielectric sidewall (SiNx or SiOx) is commonly used to offset the lateral extension of the p-implant underneath the gate of the HFET or the emitter of the HBT and also allow "enough" margin for the expected lateral diffusion upon annealing (Figs. 1a and 1b).

Amorphous silicon sidewall is used in this experiment to replace the conventional nitride or oxide sidewall. Thus, during the p- implant some silicon atoms are recoiled from the sidewall into the (Al,Ga)As (undoped insulator for the HFET or n-doped emitter for the HBT). This creates an excess charge of n-type dopants in the (Al,Ga)

(Image Omitted)

As region underneath the sidewalls upon annealing. Consequently, the lateral p-n junction plane, which is defined as the point of conversion from undoped (for HFET) or n-type (Al,G...