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Three-Level Memory Structure for Performance-Oriented Machine Code Placement

IP.com Disclosure Number: IPCOM000035982D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 90K

Publishing Venue

IBM

Related People

Doettling, G: AUTHOR [+4]

Abstract

The processing unit (PU) supports a control store address space of 64k. Different criteria with regard to performance and accessibility have made it necessary to distribute the microcode in three separate storage media: 1) a high-performance part located in a fast RAM, 2) a medium-performance part located in the main store, and 3) a slow-performance part located in a non-volatile store (EPROM).

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Three-Level Memory Structure for Performance-Oriented Machine Code Placement

The processing unit (PU) supports a control store address space of 64k. Different criteria with regard to performance and accessibility have made it necessary to distribute the microcode in three separate storage media: 1) a high-performance part located in a fast RAM,

2) a medium-performance part located in the main

store, and

3) a slow-performance part located in a non-volatile

store (EPROM).

The PU performs microinstructions always from the control store CS. The microcode which cannot be held resident in the control store is executed from the control store buffer CS-BUFFER.

The CS-BUFFER is logically separated from the control store but may be physically located therein. It represents a 64-byte-wide intermediate storage for the microcode which is located in the main store or in the EPROM. DESCRIPTION OF CONCEPT

The total CS address range is 64k, the low-order 16k being re served for the fast control store RAM. For cost/performance reasons, the control store RAM has a limited size and is reserved for performance-critical microcode.

Any address above the available CS size leads to a CS-BUFFER access. The bits 11 - 15 of the address contained in the control store address register CSAR are used to address 32 halfwords of the CS-BUFFER; a microinstruction is 2 or 4 bytes long. The bits 0 - 10 of the address contained in the CSAR are compared with the bits 0 - 10 of the buffer address compare register BACR.

In the case of a match, the accessed microinstruction from the CS- BUFFER is loaded into the destination register which is mostly the operation register. The microinstruction fetch from the control store and the control store buffer is performed in one cycle.

In the case of a mismatch, a forced operation, called FOP transfer, is initiated. The CS-BUFFER is loaded with 64 bytes from the internal object area IOA of the main store. The respective main store address for the IOA is assembled from the CSAR and a pointer, called microcode origin MCO, which is fetched from a work register in the data local store. The pointer is loaded by microcode in the initial microprogram load IML phase. This allows a certain degree of flexibility for placing the microcode which is located in the main store. The CS address range is limited to 64k halfwords, but a larger space may be used by changing the contents of the MCO register.

After completion of the FOP transfer, the CS-BUFFER contains valid microinstructions, the BACR is set to that specific address range, and the PU continues with the execution of the microinstructions until the next mismatch occurs.

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DESCRIPTION OF EXTENDED CONTROL STORE ADDRESS SPACE: A new dimension of accessing microcode was introduced in response to the requirement to initialize the system without the help of a support processor. In addition, code for new functions had to be added. The solution was found by adding another 64k address...