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Fault-Tolerant Key Arrays

IP.com Disclosure Number: IPCOM000035990D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Hanrahan, DJ: AUTHOR [+3]

Abstract

Disclosed is a method of operating a fault-tolerant key array which increases the retriability of failing storage operations involving implicit and explicit storage protection key accesses. The method involves storing a protection key in both primary and secondary key arrays in certain system configurations without additional product cost and maintaining one single key array part number. The secondary key arrays become the redundant backup key arrays for predefined storage address ranges.

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Fault-Tolerant Key Arrays

Disclosed is a method of operating a fault-tolerant key array which increases the retriability of failing storage operations involving implicit and explicit storage protection key accesses. The method involves storing a protection key in both primary and secondary key arrays in certain system configurations without additional product cost and maintaining one single key array part number. The secondary key arrays become the redundant backup key arrays for predefined storage address ranges.

On a subsequent fetch of a protection key from the array, if a machine check is detected in the key arrays, the recovery action will be invoked. The recovery procedure will attempt to refresh the failing protection key entry with good key data from the secondary array for soft errors to facilitate the instruction retry. For hard errors detected in the arrays, the secondary will be switched to become the primary key array and the system can continue without disruption.

The figure shows a 64MB system memory configuration. Since there is a storage key for every 4K page of memory, 16,384 storage keys must be placed in the key array. The Key array data is stored in 2 chips each having 2 4KX9 arrays. The first array holds keys up to 16MB, the second array holds from 16MB up to 32MB, the third 32MB up to 48MB, and the fourth 48MB up to 64MB.

The hardware design has been implemented such that the address/ commands for each key operation are decoded at each of t...