Browse Prior Art Database

Serial Multiprocessing Architecture for Signal Processing

IP.com Disclosure Number: IPCOM000036006D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR

Abstract

This disclosure is Signal Processing oriented and all the processors used here are based on the HARVARD architecture, i.e., all processors have separate instruction memories and working memories.

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Serial Multiprocessing Architecture for Signal Processing

This disclosure is Signal Processing oriented and all the processors used here are based on the HARVARD architecture, i.e., all processors have separate instruction memories and working memories.

Let us first consider two processors coupled to the same working memory and with separate instruction memories (Fig. 1). Due to the fact that the working memory is a double port memory which permits the two processors together to access the same data bank, data communication is facilitated. No contention appears in the data bus because there is one data bus for each processor.

Let us now consider several processors coupled two-by-two to the same working memory (Fig. 2). The processor-N can communicate to the Memory N and the Memory N+1, the two memories are memory address mapped and the data buses from Memory N and Memory N+1 are multiplexed at the processor input.

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All processor communications are made through the memory using flags or semaphores.

Assuming that tasks can be executed in serial, an improved architecture is therefore proposed based on a basic processor cell (Fig. 3) which is duplicated many times and serialized.

It includes the processor, its associated instruction memory and the double port RAM. It is like a quadripole with 2 inputs and 2 outputs. The 2 outputs are connected to the 2 inputs of the next cell, so that a continuous chain can be implemented.

In this case, if the base pro...