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Single-Crystal Silicon Embedded With Insulated Conducting Wires

IP.com Disclosure Number: IPCOM000036028D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Related People

Lu, NC: AUTHOR [+2]

Abstract

In packaging technology, a generic problem is that the packaging materials tend to have a different thermal expansion coefficient from that of silicon. Consequently, upon thermal cycling during operation a shear stress is exerted on those solder balls that join the chip and module, and fatigue failure of the balls occurs. This problem limits the size of the chip since the magnitude of the shear depends on the chip size. In order to overcome this problem so that a large chip can be used in VLSI, there has been a long term effort to develop ceramics which have the same thermal expansion coefficient as that of silicon. However, the material which has the best match of expansion coefficient with silicon is silicon itself.

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Single-Crystal Silicon Embedded With Insulated Conducting Wires

In packaging technology, a generic problem is that the packaging materials tend to have a different thermal expansion coefficient from that of silicon. Consequently, upon thermal cycling during operation a shear stress is exerted on those solder balls that join the chip and module, and fatigue failure of the balls occurs. This problem limits the size of the chip since the magnitude of the shear depends on the chip size. In order to overcome this problem so that a large chip can be used in VLSI, there has been a long term effort to develop ceramics which have the same thermal expansion coefficient as that of silicon. However, the material which has the best match of expansion coefficient with silicon is silicon itself.

In order to use silicon as a packaging material, it must be possible to lay conducting wires and vias within it, same as with the multi-layered ceramic (MLC) substrates used today. To achieve this, a method is described to construct a three-dimensional network of insulated conducting lines within a single-crystal silicon. The procedure for the construction of a wire is illustrated in Figs. 1A - 1F, and of a via in Figs. 2A - 2G.

(Image Omitted)

Wire Construction

A line trench 10 is first etched in silicon layer 12. Fig. 1A shows the trench 10 (the cross-section of a line) having a lining 14 comprised of SiO2/Si3N4/SiO2 .

Fig. 1B shows the conformal deposition of a conducting material 16, such as W containing about 5 at .% of Si, or W Si2 containing about 5 at .% excess Si.

Fig. 1C shows planarization of the surface by chemical and mechanical polishing and etching away the excess W alloy or silicide.

Fig. 1D shows oxidation of the W alloy or silicide to produce a thick layer 18 of SiO2 on top of the line 20. Because SiO2 is thermodynamically more stable than the oxides of W, it will form on the surface of the line. The composition of Si in the W alloy or silicide line 20 is chosen so that a thick SiO2 layer 18 can grow on the wire surface.

Fig. 1E shows that by chemical etching, the oxide and nitride on the Si surface are removed. Because the oxide 18 on the line is thick, a layer of SiO2 will survive the etching and insulate wire 20.

Fig. 1F shows that by epi-Si and SOI (Si on Insulator) growth, a Si layer 22 can be grown on the wire in a single crystal Si environment.

This procedure can be repeated to produce a second layer of wires. Nevertheless, vias or through-holes are needed between them for interconnection.

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Via Construction: Fig. 2A shows the growth or deposit of a thick thermal SiO2 layer 24 on the surface of Si layer 26. By lithographic patterning, via hole 28 is opened in the oxide by etching, after which reactive ion etching is used to drill a via in the Si 26. Drilling stops at the bottom oxide surface of the via. Fig. 2B shows the growth of a sidewall oxide 30 on the via. Some oxide growth will occur simultaneously on the surfa...