Browse Prior Art Database

Chip Design Exclusively by Programs

IP.com Disclosure Number: IPCOM000036035D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Anderson, H: AUTHOR [+4]

Abstract

VLSI logic chips are placed and wired by using suitable programs. Overlay checks ensure that books are not using the same chip area.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 3

Chip Design Exclusively by Programs

VLSI logic chips are placed and wired by using suitable programs. Overlay checks ensure that books are not using the same chip area.

A significant portion of the shape data is provided by the chip image. This contains the power distribution in the first and the second metal and all silicon shapes that are independent of book placements. For gate arrays, for example, all silicon shapes are part of the chip image.

VLSI chips should be flexible to include standard components, such as RAMs (read-only memories) or PLAs (programmable logic arrays), in their design without problems. Such components have unique silicon shapes and their own power distribution. The gate array in the respective chip area must be interrupted for their placement. Presently, a new chip image and a set of associated rules have to be generated every time such components or macros are placed.

The following procedure is proposed. All production shapes are provided by books. Recurring elements of the chip image are defined in books without logical functions. The placement capability of present programs is used to construct the chip image production shapes. The figure shows the respective chip elements and where they are used in the chip image. Table of different types of elements and their use in the chip: Element Use in chip

1) internal array element matrix (row x column)

2) horizontal I/O cell 2 columns

3) vertical I/O cell 2 rows

4) corners 4 locations

The chi...