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AC Quality Improvement of BI-CMOS Integrated Circuits

IP.com Disclosure Number: IPCOM000036036D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+6]

Abstract

A method is described that improves the quality level of BI-CMOS integrated circuits by reducing the number of AC failures which are not detected by DC testing. Fig. 1 shows the conventional way of connecting devices in a standard BI-CMOS logic gate, used here as a typical example. Several devices in such a gate have been introduced for speed improvement only. Consequently their operation is not checked by DC functional testing.

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AC Quality Improvement of BI-CMOS Integrated Circuits

A method is described that improves the quality level of BI-CMOS integrated circuits by reducing the number of AC failures which are not detected by DC testing. Fig. 1 shows the conventional way of connecting devices in a standard BI-CMOS logic gate, used here as a typical example. Several devices in such a gate have been introduced for speed improvement only. Consequently their operation is not checked by DC functional testing.

One can notice, for instance, that the output can be pulled up by the base- emitter junction of T1 even if the collector of T1 is not at VH. Also, the base of T1 does not need to be pulled down by the N1-N2 stack to get a down level on the output. Likewise, OUT can be pulled down by the N3-N4-NX stack if the collector contact on T2 is missing.

All these defects dramatically slow down the circuit but do not prevent the concerned chip from showing good operation at DC testing.

Fig. 2 describes an improved device implementation that reduces the number of such AC failures not detectable by DC testing. This new implementation is governed by the principle that any defect which can create an AC fault must also create a DC fault. Its efficiency level relies on the high occurrence rate of defects due to open connections in VLSI chips (open contacts, open vias or open metal). The method consists in putting the anticipated open defect in series with a device which is indispensable to the DC operation. For instance:

The collector contact and connection of T1 has been put in series with the dr...