Browse Prior Art Database

DTE Clock Generation for High Speed Modems

IP.com Disclosure Number: IPCOM000036039D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR [+2]

Abstract

As illustrated in Figure 1, the disclosed invention is a circuit which generates the data terminal equipement (DTE) clock signals. Such a circuit is characterized by the fact that the DTE counters, receive or transmit, are each split into two counters. One counter has a period which depends only upon the baud rate (baud-dependent counter), and one counter depends upon the number of bits per baud (PLO counter).

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DTE Clock Generation for High Speed Modems

As illustrated in Figure 1, the disclosed invention is a circuit which generates the data terminal equipement (DTE) clock signals. Such a circuit is characterized by the fact that the DTE counters, receive or transmit, are each split into two counters. One counter has a period which depends only upon the baud rate (baud-dependent counter), and one counter depends upon the number of bits per baud (PLO counter).

The counter which depends upon the baud rate can have 4 periods, selectable through microcode actions. For a baud rate of 2400 Hz, the length of the baud-dependent counter is 60. For a baud rate of 1600 Hz, the length of the baud-dependent counter is 90. For a baud rate of 1200 Hz, the length of the baud-dependent counter is 120. For a baud rate of 600 Hz, the length of the baud-dependent counter is 240.

The PLO counter has a length of 18, except when phase-locked oscillator (PLO) variations are initiated. In this case, the length of the PLO varies from 15 to 21 steps. If b is the number of bits per baud, the PLO counter generates b pulses every period of 18 steps.

The purpose of this invention is to generate a set of DTE clocks with the following constraints:
1. All DTE clocks are derived from a single clock (clk1).

The frequency of clk1 is osc1. In the example, osc1

equals 2,592 megahertz.
2. The phase of all DTE clocks must be adjusted with only

one microcode operation, or, in other words, by

updating the contents of only one register.
3. Some of the frequencies of the DTE clocks are not

multiples of osc1.

All DTE clocks are generated by two counters connected in series. The first counter (C1) increments with every period of clk1. The second counter (C2) increments with every carry of C1. The length of first counter is related to the number of bits per ba...