Browse Prior Art Database

Pipelined Clocked Static Memory

IP.com Disclosure Number: IPCOM000036040D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+2]

Abstract

Fig. 1 shows a conventional data path of a synchronous static memory. The array clock generates specific pulses in the timing chain which are used for the internal circuits. The only difference with this data path is that the word line driver is replaced by a word line latch.

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Pipelined Clocked Static Memory

Fig. 1 shows a conventional data path of a synchronous static memory. The array clock generates specific pulses in the timing chain which are used for the internal circuits. The only difference with this data path is that the word line driver is replaced by a word line latch.

The word line latch is shown in Fig. 2, where only two devices T1 and T2 are added from the original word line driver. These two devices are controlled by an isolation clock IS. A down level of IS isolates the word line from the decoding stages and latches the word line.

Upon completion of decoding, the respective word line is latched and isolated from the decoding stage. During sensing and amplification, the isolated decoder may be restored while a new cyle is started.

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This small modification of an existing design reduces the cycle time drastically and improves the processor performance for a cache application.

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