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Complementary Bi-Cmos XOR/XOR-NOT Circuits With Built-In Inverters

IP.com Disclosure Number: IPCOM000036041D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+3]

Abstract

XOR circuits can be built with Bi-CMOS technology in two layers of logic function. In the standard XOR 2 ways shown in Fig. 1, the first layer is made with CMOS inverters and the second one with AND-OR-Inverter Bi-CMOS circuits. Some improvements have been made to reduce the number of FET transistors and to speed up the circuit for lower power dissipation. In that respect, Figs. 2 and 3 show respectively Bi-CMOS XOR2 and XNOR2 with built-in inverters.

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Complementary Bi-Cmos XOR/XOR-NOT Circuits With Built-In Inverters

XOR circuits can be built with Bi-CMOS technology in two layers of logic function. In the standard XOR 2 ways shown in Fig. 1, the first layer is made with CMOS inverters and the second one with AND-OR-Inverter Bi-CMOS circuits. Some improvements have been made to reduce the number of FET transistors and to speed up the circuit for lower power dissipation. In that respect, Figs. 2 and 3 show respectively Bi-CMOS XOR2 and XNOR2 with built-in inverters.

Due to the fact that the complementary Bi-CMOS XOR/XOR-NOT have their CMOS circuits tied to GND or VH, it is possible to integrate the FET's devices of the two CMOS inverters in the final AND-OR-Inverter circuits with the existing devices. This can be done for the XOR as well as for the XOR-NOT function. In the XOR circuit shown in Fig. 2, the NFET's N1 and N2 perform the same AND logic function as N3 and N4 with inverted inputs to have the NFET's N2 tied to the GND with B input and the NFET's N4 also tied to GND with the A input. The N1, N2, N3, N4 FET transistors are supposed to be the half size of N5 and N6 to have symmetrical output signals. The CMOS inverters are built with P3 and N4 to generate the A complementary input and with P1 and N2 for the B complementary input.

Fig. 3 represents an XOR-NOT circuit built with the same concept. In this case, the top PFETs (P1 and P2) are duplicated (P3 and P4) instead of the bottom NFETs (N1 and N2) for t...