Browse Prior Art Database

Phase-Locked Oscillator Repartitor for High Speed Modems

IP.com Disclosure Number: IPCOM000036053D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR [+2]

Abstract

This invention prevents the relative receive clock period variations in a 19, 200 bps modem from being too important for certain types of data terminal equipement.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Phase-Locked Oscillator Repartitor for High Speed Modems

This invention prevents the relative receive clock period variations in a 19, 200 bps modem from being too important for certain types of data terminal equipement.

In Fig. 1, the phase-locked oscillator (PLO) circuit consists of a modulo 18 counter (C0) associated with control circuits (CTL). The counter (C0) is incremented with a free-running clock (clk0) of frequency equal to 2,592 megahertz. The output of C0 increments a modulo 60 counter C1. The output of C1 is a pulse of 2400 Hz (receive baud pulse). The free-running clock (clk0) also increments four counters Ca, Cb, Cc and Cd which respectively deliver the receive clock on DTE ports A, B, C and D. For synchronization purposes, the receive baud pulse resets the four counters Ca..Cd.

The length of C0 expressed in number of steps, may fluctuate. During one period, the length of C0 can increase or decrease by 3 steps. In that case, the output of C0 shifts backward or forward by a duration of 3 times st0 = 1/2,592 microsecond. The receive baud pulse, and the four DTE receive clocks follow the above shift variation.

If the frequency of the DTE receive clock from port A equals 19,200 Hertz, the length of counter Ca is 135. After a PLO action, one period of DTE receive clock A is modified from 135 times st0 to either 132 or 138 times st0. So, the relative variation of the DTE receive clock period is 3/135 = 2.22 %.

(Image Omitted)

This variation is too high for some DTEs, and a rx PLO distributor circuit is necessary to solve this specific problem.

The receive PLO distributor consists of a 5-bit serial-in/parallel-out shift register (SH) associated with...