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Array Card With Partially Good Array Modules

IP.com Disclosure Number: IPCOM000036061D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Barbash, WA: AUTHOR [+2]

Abstract

In the design of computer storage, large numbers of array elements (modules) are often interconnected in a two-dimensional (address X I/O) matrix on an array card. In applications where economic factors outweigh density considerations, it can be desirable to use array modules that are imperfect in a predictable manner. One type of partially good module has M addresses by N input/output (I/O) lines, where P out of N I/O lines are "good". Since there are many possible combinations of partially good modules that can occur, the conventional way to make use of these modules is to design a unique array card interconnection pattern for each type of partially good array module.

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Array Card With Partially Good Array Modules

In the design of computer storage, large numbers of array elements (modules) are often interconnected in a two-dimensional (address X I/O) matrix on an array card. In applications where economic factors outweigh density considerations, it can be desirable to use array modules that are imperfect in a predictable manner. One type of partially good module has M addresses by N input/output (I/O) lines, where P out of N I/O lines are "good". Since there are many possible combinations of partially good modules that can occur, the conventional way to make use of these modules is to design a unique array card interconnection pattern for each type of partially good array module.

This disclosure achieves the following:

1. Only one card personality is required for each

combination of P out of N "good" I/O.

(Image Omitted)

2. The set of modules forming each combination of P

out of N "good" I/O can be randomly placed on the

array card,

alleviating supply, assembly and test problems.

3. The array card configuration of "good" module I/O

lines can be determined after assembly.

4. All assembled array cards of a particular P out of

N type are functionally equivalent and

interchangeable.

The following is the disclosed design of the array card:

1. Populate an array card with array modules that are

N bits wide in the I/O dimension, where N is

greater than 1.

2. Permit all the combinations of either the half

"good" or the three-quarter "good" modules to be

randomly placed on the card (half "good" and

three-quarter "good" modules are not mixed on the

same card).

3. Steer the array I/Os through logic to the speed

matching buffers that are directed by either:

a) the card map placed in a PROM (programmable

read-only memory) at card assembly test time;

or

b) the card map stored in a RAM (random-access

memory) or latches at power-on time based on

either the

1) values determined by a self

reconfiguration operation; or

2) values previously saved in a power-on

processor. The following assumptions

have been made:

1. For the case where the card map is determined at

1

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power-on time via self-reconfiguration, all of the

partially "good" modules have their "bad" outputs

permanently disabled to a given state. This will

minimize the rest time at power-on.

2. For the case where t...