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Generic Burn-In for LOCST Chips

IP.com Disclosure Number: IPCOM000036074D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Storey, TM: AUTHOR

Abstract

Semiconductor components for military purposes must be burned-in prior to shipment due to military standards. This burn-in can represent a significant additional cost, since unique burn-in cards are required for each component. The problem is further exacerbated in CMOS where it is generally felt the only suitable burn-in environment is one in which there is a constant interval switching activity known as dynamic burn-in. A dynamic burn-in oven can cost up to ten times the cost of a normal (static) burn-in oven. This article describes a generic burn-in configuration whereby chips can be tested using a static oven burn-in configuration in a dynamic manner.

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Generic Burn-In for LOCST Chips

Semiconductor components for military purposes must be burned-in prior to shipment due to military standards. This burn-in can represent a significant additional cost, since unique burn-in cards are required for each component. The problem is further exacerbated in CMOS where it is generally felt the only suitable burn-in environment is one in which there is a constant interval switching activity known as dynamic burn-in. A dynamic burn-in oven can cost up to ten times the cost of a normal (static) burn-in oven. This article describes a generic burn-in configuration whereby chips can be tested using a static oven burn-in configuration in a dynamic manner.

The invention takes advantage of the already existing self-test logic on the CMOS chip during burn-in. The current implementation of self-test uses LSSD latches in combination with an embedded pseudorandom pattern generator and an embedded multiple input signature register to generate and collect the internal states. This approach is known as LSSD On Chip Self-Test (LOCST).

Referring to Fig. 1, each burn-in board is designed to route each input and output of every socket to the configuration card. The design is the same whether a given chip pin is an output, input or a common

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I/O. In each case, the same pin per socket is wired to the corresponding pin on the other sockets and this common net is fed through a resistor on the configuration board. This commonality is possible, because the chip will be in self-test mode during burn-in.

In self-test mode, the signals of the chip can be divided into four classes: 1) self-test control inputs, which must be held to one or zero to enable self-test, 2) self-test clock input, which uses the imbedde...