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Pulse Width Repeater Circuit for Data Separator

IP.com Disclosure Number: IPCOM000036077D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Swart, DP: AUTHOR

Abstract

This circuit duplicates the width of an input pulse after the input pulse has ended. An input pulse of width W causes a capacitor to charge in one polarity. At the end of the input pulse, the capacitor current reverses direction and an output pulse is initiated. When the capacitor voltage has returned to its original value, the current stops and the output pulse ends. Since the discharge rate equals the charging rate, the width of the output pulse is equal to the width of the input pulse.

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Pulse Width Repeater Circuit for Data Separator

This circuit duplicates the width of an input pulse after the input pulse has ended. An input pulse of width W causes a capacitor to charge in one polarity. At the end of the input pulse, the capacitor current reverses direction and an output pulse is initiated. When the capacitor voltage has returned to its original value, the current stops and the output pulse ends. Since the discharge rate equals the charging rate, the width of the output pulse is equal to the width of the input pulse.

The differential input to the circuit of Fig. 1 is applied to amplifier Q1-Q2. The amplified signal at node 3 is downshifted by Q4, D1, Q5, R4, and R5 and applied to the base of Q6. Q6 inverts this signal and produces a large (4-volt) voltage swing at node 10. The large voltage at node 10 enables this circuit to generate large amplitude voltage ramps at nodes CAPL and CAPR.

During the quiescent state, input IN is at a Down level compared to input NIN. Fig. 2 shows the circuit waveforms. This puts node 3 at a Down level, so Q6 is off. Therefore, node 10 is at its Up level, i.e., equal to the positive supply voltage (+5 volts).

(Image Omitted)

Node 10 drives Q8, which holds node CAPL at a constant 4.2 volts. During the quiescent state, there is no current in the capacitor C1 connected between nodes CAPL and CAPR, and the current sunk by current source Q9 (0.5 ma) is pulled through R17. The voltage developed at node 33 is then 0.05 volts below the +5-volt rail.

On the other side of the capacitor, the base of Q10 is biased at a fixed 3.6 volts by R12 and D5. Therefore, node CAPR is fixed at 2.8 volts. Again, there is no current in the capacitor C1, so the 0.5 ma sunk by Q11 is pulled through R10.

Note that R10 is twice the value of R17, so the voltage at node 15 is 0.10 volts below the +5 volt rail, compared to only 0.05 volts below the rail at node 33. This difference in voltages is amplified by differential stage Q13-Q14 to produce a Down-level output at node OUT and an Up level at node NOUT for the quiescent state.

When an input pulse is applied, node IN goes to its Up level (and NIN goes to its Down level), causing Q6 to turn on. Node 10 is pulled down to +1 volt and Q8 is turned off. The voltage at node CAPL now begins to ramp down due to the 0.5 ma being pulled through the capacitor C1 by Q9.

Meanwhile, node CAPR is still held at its constant value of 2.8 volts. The current sunk by Q9 now is pulled through R10, Q10, and the capacitor C1. Now the current in R17 has gone to zero while the current in R10 is doubled to 1.0 ma. But node 15 is still more negative than node 33, so the output at nodes OUT/NOUT has not changed state.

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Node CAPL continues to ramp down until the input pulse ends. Input pulse width W is not predictable, so th...