Browse Prior Art Database

Switched Bus for High-Performance Multi-Processor Systems

IP.com Disclosure Number: IPCOM000036078D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Harrison, CG: AUTHOR

Abstract

In a conventional, bus-based computer, each card slot is directly connected to the bus wiring. Communication on the bus occurs as sequential dialogues between pairs of cards connected to the bus. In multi- processor systems, the contention for the bus among a large number of cards may be a limiting factor on the overall performance of the multi- processor.

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Switched Bus for High-Performance Multi-Processor Systems

In a conventional, bus-based computer, each card slot is directly connected to the bus wiring. Communication on the bus occurs as sequential dialogues between pairs of cards connected to the bus. In multi- processor systems, the contention for the bus among a large number of cards may be a limiting factor on the overall performance of the multi- processor.

In this invention, the bus is replicated to provide 4, 8 or more sets of bus wiring. Each card slot is connected to each of the sets of bus wiring via logic switches with the exception of the common bus request/bus grant wiring which is routed directly from the card slots to the bus arbiter. The bus structure is replicated in additional wiring layers in the backplane. The switch logic is incorporated on the backplane. No modification is required to the cards used in the backplane and the switching of the bus is transparent to the cards. However, it does require that the arbiter be informed of the system memory map, since it needs to know the correspondence between the addresses and card slots.

The switched bus operation is broadly as follows:

1. A card requiring bus access queries the bus request

line.

2. If the bus request line is busy:

a. The requesting card waits until the bus

request line becomes free and then proceeds

as below.

3. If the bus request line is free:

a. The requesting card signals a bus request to

the arbiter.

b. The arbiter flags that card slot as active.

c. The arbiter determines whether any set of bus

wiring is free.

d. If no bus is currently free:

1) The request is queued at the arbiter

until a bus becomes free and then

proceeds as below.

e. If there is a free bus:

1) The arbiter causes the bus switch for

that card slot to select the free bus

and issues a bus grant to the card slot

but maintains the bus request line busy.

Continued:

2) The requesting card places the address

on the selected bus' address lines.

3) The arbiter determines whether the

corresponding card slot is active.

4) If the addressed card slot is active:

a) The access is queued u...