Browse Prior Art Database

Third Pipe-Line for a Two Pipe-Line Processor Architecture

IP.com Disclosure Number: IPCOM000036093D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR [+2]

Abstract

Widely used processors capitalize on a two pipe-line architecture for powerful features such as table look-up, multi-branches and saved address or subroutines [*]. The two pipe-lined cycles perform the instruction fetch followed by the instruction execution. As shown in Fig. 1A, during the fetch, the instruction is taken from the instruction memory and prepared for execution; the decode and the indexation calculation for data memory access are in fact made.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Third Pipe-Line for a Two Pipe-Line Processor Architecture

Widely used processors capitalize on a two pipe-line architecture for powerful features such as table look-up, multi-branches and saved address or subroutines [*]. The two pipe-lined cycles perform the instruction fetch followed by the instruction execution. As shown in Fig. 1A, during the fetch, the instruction is taken from the instruction memory and prepared for execution; the decode and the indexation calculation for data memory access are in fact made.

It is proposed thereafter to separate the real fetch from the preparation by including a third pipe-line between the two previously mentioned. We include in it the instruction decode and the indexation calculation. The main purpose for this is the execution speed increasing or the capability to use slower instruction memories. The problem of code compatibility and the conservation of the feature advantage require that this third pipe-line be transparent to the programmer. The number of pipe-line is visible only during branching. If the branch is taken, the pipe-line must be emptied, so generally the instructions following it are always executed. One instruction is always executed from a two pipe-line architecture (B+1), two instructions for a three pipe-line architecture (B+1 and B+2), and so on. In our case, the first instruction after the branch is well known to the programmer and by the program tools. The purpose of this proposition is to make secre...