Browse Prior Art Database

Off-Chip Module Clock Controller

IP.com Disclosure Number: IPCOM000036096D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Cady, AM: AUTHOR [+2]

Abstract

This article relates to independent clock control of a chip in a system level environment where the chip clocks are connected to a common system clock. This feature permits one or more chip clocks to be placed into a self-test or stop mode while the remainder of the chip clocks continue to operate normally.

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Off-Chip Module Clock Controller

This article relates to independent clock control of a chip in a system level environment where the chip clocks are connected to a common system clock. This feature permits one or more chip clocks to be placed into a self-test or stop mode while the remainder of the chip clocks continue to operate normally.

In the figure, an On-Chip Monitor Clock Controller (OCC) 10 uses the bus instructions to an On-Chip monitor (OCM) 12 to enable, disable, and single cycle a chip's internal clocks. The OCC generates three signals for use by a chip designer. The signals are: Inhibit System C Clock 14; Enable System B Clock 16 and Enable Scan B Clock 18. These signals correspond to the control signals used by a cross-coupled driver 20 for all chip clocks.

A key element in the OCC is an Enable Clock Register (ECR) 22. When this register is set to a value of "1", the clock signal 16 is active and the clock signal 14 is inactive. In this state, the system B clock 24 and the system C clock 26 are distributed through the driver 20 to the logic on the chip (not shown). In order to disable the chip clocks, a zero must be written into the ECR. This is done by having the OCM send out a zero on User Defined Line (UDF) 28 and a "1" on its UDF Line 30. When the ECR is at a "0" state, the inhibit clock 14 is activated and the enable clock 16 is deactivated so that the clocks to the chips (not shown) are disabled. In this state, the driver 20 leaves the B clock 24 active and the C clock 26 inactive when it is disabled.

The OCM can be instructed to perform a scan operation on the chip with the data coming fro...