Browse Prior Art Database

Distributed Switching in VLSI Devices

IP.com Disclosure Number: IPCOM000036098D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

DeBar, DE: AUTHOR [+2]

Abstract

Disclosed is a method of redistributing changes in circuit current initiated by switching off-chip drivers from changes in circuit current which occur as a result of internal device switching.

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Distributed Switching in VLSI Devices

Disclosed is a method of redistributing changes in circuit current initiated by switching off-chip drivers from changes in circuit current which occur as a result of internal device switching.

With the advent of VLSI, in which internal circuit elements are increasingly smaller and denser while the off-chip drivers (OCDs) must maintain reasonable current-carrying capabilities, noise which occurs during chip and module testing becomes a critical problem. In CMOS VLSI designs, a large current surge occurs as the OCDs change state. The effect of this current surge can be to induce unacceptably high voltage transients due to the unbypassed inductance of a chip/module tester. If the change in current is not controlled, it can cause dips or ground bounce in the voltage power supply which may alter the state of the internal logic. This unintended change in internal logic state will most likely result in a test failure, thus causing a device which would operate properly in its ultimate, more benign electrical environment, to be rejected.

The solution is to separate internal logic switching from OCD switching. This must be performed in a manner that maintains the intent of each logic pattern (which, if applied using standard timing, would cause internal and OCD switching simultaneously).

Level Sensitive Scan Design (LSSD) tests are divided into three logical phases. In the first phase, shift register latches (SRLs) are set to their desired state by serially shifting data into them. On each test vector, the scan-in to the shift register is changed, followed by the pulsing of the A and B shift clocks, which set the L1 and L2 of each SRL, respectively. Once all SRLs are assigned, the second phase begins. In this phase, the primary inputs to the chip are assigned, the system clocks are pulsed (sets the L1s), and then the shift B clock is pulsed to transfer the result of the test to the L2. In the final phase, the contents of the SRLs are made observable by serially shifting out the registers by pulsing the A and B shift cl...