Browse Prior Art Database

Functional Self-Test for a "Double Clock Path"

IP.com Disclosure Number: IPCOM000036100D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

LeBlanc, JJ: AUTHOR [+2]

Abstract

If random pattern self-test is to be used for detecting performance- related defects as well as function-related defects, "all" logic paths must be predictable for the required operating speed of the chip. By 'predictable', it is meant that the data inputs to all registers have been stabilized and can be loaded into the register on every clock cycle. In a defect-free environment, 'predictable' data are captured by all latches throughout the random pattern self-test operation, thereby providing a stable, expected pass/fail "signature". This signature can then be used to verify the integrity of other chips of the same type (i.e., part number).

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Functional Self-Test for a "Double Clock Path"

If random pattern self-test is to be used for detecting performance- related defects as well as function-related defects, "all" logic paths must be predictable for the required operating speed of the chip. By 'predictable', it is meant that the data inputs to all registers have been stabilized and can be loaded into the register on every clock cycle. In a defect-free environment, 'predictable' data are captured by all latches throughout the random pattern self-test operation, thereby providing a stable, expected pass/fail "signature". This signature can then be used to verify the integrity of other chips of the same type (i.e., part number).

However, chips that contain 'double clock paths' may not generate a predictable signature because two clock cycles are needed for known data to become stable before being loaded properly into the receiving register of the 'double clock path'. A typical solution to this problem is to merely disable the 'double clock path' registers during the random pattern self-test operation to ensure that no indeterminate states are captured. The result of this solution is that the 'double clock path' logic is NOT TESTED by the random pattern self-test operation. This article illustrates logic that will allow for the functional testing of 'double clock path' logic without jeopardizing the predictability of the random pattern self-test signature.

Referring to the figure, to execute self-test and generate a resulting signature, all registers within a chip are loaded via a scan operation. Once loaded, the system C,B clocks to all register...