Browse Prior Art Database

Internal Chip Bus Request Prioritization

IP.com Disclosure Number: IPCOM000036104D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Gercken, AF: AUTHOR

Abstract

A bus interface controller may need to request the local or system bus to perform a variety of functions. These functions include initiating a transfer, performing a commanded operation, signalling completion of a commanded operation, and reporting requested status on a previous transfer. Internal to the chip, a complex master controller is generally used to interact with every bus request function to be implemented - forcing interdependencies between all functions. A more (Image Omitted) effective approach is a simple priority scheme. This eliminates the need for a master controller and allows each bus request function to be designed and tested independently.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

Internal Chip Bus Request Prioritization

A bus interface controller may need to request the local or system bus to perform a variety of functions. These functions include initiating a transfer, performing a commanded operation, signalling completion of a commanded operation, and reporting requested status on a previous transfer. Internal to the chip, a complex master controller is generally used to interact with every bus request function to be implemented - forcing interdependencies between all functions. A more

(Image Omitted)

effective approach is a simple priority scheme. This eliminates the need for a master controller and allows each bus request function to be designed and tested independently. After individual design and testing, each bus request function can be merged with the appropriate bus request prioritization logic with high confidence in the total design. Thus, the overall design cycle time is reduced.

The key to simplifying the bus request logic is to wait until the bus is won to implement the internal prioritization. As shown in Fig. 1, the prioritization logic allows all internal functions to request the bus (the OR gate) but only notifies the highest priority function that the bus has been won. The highest priority function performs its task and all other internal functions continue to request the bus as if it has not yet been won. On the next possible contention cycle, the bus will again be requested by the remaining active internal bus requests. Because there is no idle contention cycle, bus efficiency is increased.

Internal bus requests may be reset...