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Browse Prior Art Database

Fast CMOS Two-Stage Word Decoder

IP.com Disclosure Number: IPCOM000036109D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Chao, H: AUTHOR [+2]

Abstract

A clocked two-stage CMOS decoder is proposed which requires only two PFET/NFET pairs for the final decoder: a first pair TP1, TN1 to NAND- gate the predecoded select signals WX and WY and a second pair TP2, TN2 to provide sufficient drive capability.

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Fast CMOS Two-Stage Word Decoder

A clocked two-stage CMOS decoder is proposed which requires only two PFET/NFET pairs for the final decoder: a first pair TP1, TN1 to NAND- gate the predecoded select signals WX and WY and a second pair TP2, TN2 to provide sufficient drive capability.

The combined final decoder and word line driver is selected if the input signal WX goes up, while the other input signal WY goes down. These two signals are NAND-gated by applying signal WX to the common gate of the first PFET/NFET pair TP1, TN1 (inverter) and signal WY to the source of the NFET TN1. Compared with a conventional three-stage final decoder/word line driver, this two-stage circuit has a 30% shorter delay time and requires less layout area.

This decoding scheme, consisting of predecoders X-DEC, Y-DEC and the final decoder, permits minimizing the critical delay of the entire address decoding path and yet is simple to design, as it requires only a single clock SWD without race conditions. It is especially suited for structured array macros embedded in VLSI logic chips, because it allows a quick reconfiguration of the decoder/array organization and requires a short design time.

The described circuit operates as follows. During standby, with clock SWD inactive, the predecoded lines WX and WY are at level GND and VDD, respectively. Thus, word line WL is held at ground level. Initiated by the rising edge of the set word decoder clock SWD, predecoders X-DEC, Y-DEC are enabled to...