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Fast CMOS Output Latch for a Ram

IP.com Disclosure Number: IPCOM000036114D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Clemen, R: AUTHOR [+2]

Abstract

A fast CMOS output sense/latch scheme is proposed which provides an adjustable data output hold time and does not require a critical timing edge. This is achieved by using a gated CMOS latch attached to a set/reset-type (main) sense amplifier.

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Fast CMOS Output Latch for a Ram

A fast CMOS output sense/latch scheme is proposed which provides an adjustable data output hold time and does not require a critical timing edge. This is achieved by using a gated CMOS latch attached to a set/reset-type (main) sense amplifier.

The sense amplifier is realized by a circuit which pulls up one output line ST or SC during the set phase SA, restoring it to ground during the reset phase RA.

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The output latch consists of a cross-coupled CMOS inverter pair T5/T7 and T6/T8, whose common source voltage is controlled by a clocked NFET T9. Each latch node DT/DC is provided with a pull-up PFET T1/T2 for precharging and a pull-down NFET T3/T4 for writing the latch. The pull-down NFETs are directly gated by sense amplifier output lines ST and SC.

Set latch clock SL merely serves to activate the cross-coupled NFET pair T7/T8 and to hold the data before the sense amplifier is reset by clock RA and the data carried on the sense lines becomes invalid. Precharge clock PL is used to turn off PFET pair T5/T6 so that the latch nodes are overwritten quickly. The data-out valid time is defined by appropriate PL timing.

The described circuit operates as follows: During standby, the output latch contains data from the preceding read cycle, although the sense lines are reset to ground.

At the start of a read cycle, set latch clock SL goes inactive and precharge clock PL pulls up both latch nodes to VDD. This clears the latch and causes the old data to become invalid. The latch is then ready to accept new data with a fast set time.

As soon as one sense line (say, ST) has reached a threshold voltage VTN, latch write device T3, in response to clock SA, turns on, discharging both the associated latch node DT...