Browse Prior Art Database

High Density Wiring Process

IP.com Disclosure Number: IPCOM000036119D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 223K

Publishing Venue

IBM

Related People

Stanasolovich, D: AUTHOR [+2]

Abstract

A major obstacle to further increases in the circuit density is the overlay tolerance associated with the alignment of each via level to the previous metal interconnect level. This tolerance and its associated borders consumes a substantial amount of circuit wiring area. In addition, the use of separate photo levels for the vias and the metal interconnects necessitates additional exposure systems, more extensive processing, and a greater yield loss due to defects caused by increased processing. This article discusses a process technology that produces a self-aligned via stud-metal interconnect structure that reduces the problems discussed above.

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High Density Wiring Process

A major obstacle to further increases in the circuit density is the overlay tolerance associated with the alignment of each via level to the previous metal interconnect level. This tolerance and its associated borders consumes a substantial amount of circuit wiring area. In addition, the use of separate photo levels for the vias and the metal interconnects necessitates additional exposure systems, more extensive processing, and a greater yield loss due to defects caused by increased processing. This article discusses a process technology that produces a self-aligned via stud-metal interconnect structure that reduces the problems discussed above.

The process begins following the definition of the contact windows. First, the normal thickness of 1.0 um of Al-Cu-Si-Ti M1 metallurgy is deposited by either sputtering or high temperature evaporation. Second, an equal or greater thickness of titanium is deposited by similar techniques. An alternative metal to titanium is tungsten, which can be deposited through CVD techniques. Third, the M1-Via resist mask is applied and the M1 and Via features are defined by the multiple reticle exposure technique. The exposure pattern is shown in Fig. 1. The resulting resist profile is depicted in Fig. 2.

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Fourth, the titanium and M1 features are etched by RIE using dry metal etch processes which are well known in the prior art, as shown in Fig. 3. The photoresist over the non-stud areas is re...