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Fast Fully Static RAM Data Path

IP.com Disclosure Number: IPCOM000036133D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Chao, H: AUTHOR [+2]

Abstract

A fully static CMOS RAM data path consisting of a memory cell, a multiplexer, and a read head is proposed, wherein the bit line voltage swing is limited to approximately VDD-VTn for fast signal propagation.

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Fast Fully Static RAM Data Path

A fully static CMOS RAM data path consisting of a memory cell, a multiplexer, and a read head is proposed, wherein the bit line voltage swing is limited to approximately VDD-VTn for fast signal propagation.

The memory cell contains a static latch as a basic storage element, a CMOS inverter I as a preamplifier and bit line driver, and an NFET transfer device TC as a read port for single-ended sensing. (The write port is not shown.) NFET pass device TC limits the bit line up-level to a threshold voltage VTn below the power supply voltage VDD.

The output multiplexer or bit line selector is realized by NFET transfer gates. The selected transfer device TM passes the bit line levels 0 V or VDD-VTn to the common data line DL. A minimum-size NFET bleeder device TN0 is attached to bit line BL to compensate for the subthreshold current which might otherwise charge the bit line to VDD (through cell access device TC).

The read head is a two-stage inverter chain, with the first and the second stage serving as a main sense amplifier and a load buffer, respectively. To avoid a DC current through the main sense amplifier, a PFET pull-up device TP0 is connected to the input and gated by the output of this circuit. This ensures an input up-level of VDD (in the steady state), when a level of VDD-VTn is supplied from the memory cell.

This approach allows operating the high-capacitance bit line BL at a lower voltage swing than data line DL. Compared with the conventional data path circuit having CMOS levels at all nodes, the mixed level design has a shorter delay.

The described circuit operates as follows: Assume a logical '1' is stored in the memory cell and bit line BL is at ground level following a preceding read '0' operation. Also assume word line WL is selected by an address change. With word line WL going up, access devic...