Browse Prior Art Database

Dual Bus Processor Architecture

IP.com Disclosure Number: IPCOM000036136D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 107K

Publishing Venue

IBM

Related People

Millas, RJ: AUTHOR

Abstract

This article describes a processor system arrangement consisting of a single processor with two sets of data, address and control buses and a separate set of instruction memory buses. The two sets of buses are used to access memory and input/output (I/O) devices located in the same memory map simultaneously.

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Dual Bus Processor Architecture

This article describes a processor system arrangement consisting of a single processor with two sets of data, address and control buses and a separate set of instruction memory buses. The two sets of buses are used to access memory and input/output (I/O) devices located in the same memory map simultaneously.

Typical processor systems consist of a processor with an address bus, a data bus, and a control bus connecting it to memory and I/O devices. Systems such as this are of Von Neumann architecture, that is that the instructions are stored in the same format and memory as is data. A slight variation of this basic architecture is to separate the instruction memory buses from the data memory buses. This permits the fetching of instructions at the same time instructions are executed and data transferred by the address, data and control buses. Architectures such as this are used in digital signal processors, where instruction speed is critical.

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A dual bus processor architecture (DBPA) is disclosed herein as shown in Fig. 1. The DPBA consists of a single processor with two sets of data, address and control buses. A separate set of instruction memory buses is also included for increased performance. The main difference from the above described systems is in the dual bus set. The two sets of buses are used to access memory and I/O devices located in the same memory map simultaneously. Bus set A can access (read or write) to any location at the same time bus set B is accessing (reading or writing) any location. The only exception being, that bus set A and bus set B cannot access the same location due to contention.

A DBPA processor can read from two locations simultaneously. Fig. 2 illustrates a basic internal view of such a processor. There are two sets of internal register banks. One bank is accessible by bus set A, the other by bus set B. These registers are used as user registers or as accumulators. When a read is performed from two locations, the contents from those locations are placed in selected registers within

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their corresponding register bank. Therefore, a read from two locations can be performed in only one machine cycle. Similarly, a DBPA processor can write to two separate locations simultaneously. Data contained in registers within the register banks are written to two separate locations in only one machine cycle.

A move from one location to another can also be performed in one machine cycle. For example, address bus A accesses the location of where the data will be moved from. Address bus B accesses the location of where the data will be moved to. Control bus A performs a read operation, and control bus B performs a write operation, thereby transferring the data through the data buses to its destination, all in one machine cycle.

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Indirect addressing, as illustrated in Fig. 3, is enhanced with this architecture. For example, address bus A accesses...