Browse Prior Art Database

Interleave Method for Cache Address Lines

IP.com Disclosure Number: IPCOM000036146D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Dixon, JD: AUTHOR [+4]

Abstract

This article describes a method which provides for one gate array circuit to interface with a cache random-access memory (RAM) and allows operation with many different sizes of RAM without having to use external pins to select modes of operation of the gate array chip.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Interleave Method for Cache Address Lines

This article describes a method which provides for one gate array circuit to interface with a cache random-access memory (RAM) and allows operation with many different sizes of RAM without having to use external pins to select modes of operation of the gate array chip.

Dynamic RAMs are internally arranged in row and column form, where the number of rows equals the number of columns. To save I/O pins and module size, the row address and column address are multiplexed, that is, they are both presented to the same pins on the RAM module, but at different times. Typically, the lower half of the address bits are used for the row and the upper half are used for the column. Fig. 1 is an example of RAM addressing. It shows a 20-bit address used with a 256K memory module. Only 18 of the address bits can be used directly, since the module has only 9 rows and 9 columns. The other two bits are either used to select a bank of modules or are ignored.

A problem occurs when the size of the memory module is changed. If the design requirements changed such that 64K became the base module size, simply swapping out the 256K modules and replacing them with 64K ones would cause a severe problem. Address bit 8 would be unconnected, and that would cause a "hole" in the address space. All 64K of storage would still be accessible, but that storage would be discontinuous, causing problems to the operation of the circuit and the software. For

(Image...