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Browse Prior Art Database

Video Subsystem Supporting Multiple Image Planes, Priority and Windowing

IP.com Disclosure Number: IPCOM000036162D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Barrera, DD: AUTHOR [+4]

Abstract

Disclosed is a device that adds the capability of priority and windowing to a system that supports transparency and the concept of a "start point" for a display frame buffer. The combination of these four capabilities allow: the formation and change of composite pictures on a display screen in real time; use and manipulation of different forms of display data independently. (Image Omitted)

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Video Subsystem Supporting Multiple Image Planes, Priority and Windowing

Disclosed is a device that adds the capability of priority and windowing to a system that supports transparency and the concept of a "start point" for a display frame buffer. The combination of these four capabilities allow: the formation and change of composite pictures on a display screen in real time; use and manipulation of different forms of display data independently.

(Image Omitted)

Fig. 1 shows a high level view of the invention. This particular implementation shows three image planes; the concept is extendable to a larger number. In this example, image plane 1 can produce either a 16 bit pel or an 8 bit pel; image plane 2 can produce either a 16 bit pel or an 8 bit pel; image plane 3 produces an 8 bit pel. In the figure, P116 and P216 represent 16 bit pel streams from image plane 1 and 2, respectively; P18 and P28 represent 8 bit pel streams from image plane 1 and 2, respectively. P3 represents an 8 bit pel stream from image plane
3. The signals ZP116, ZP216, ZP18, ZP28 and ZP3 indicate that a pel in the respective pel stream is transparent; these signals feed the logic in Fig. 2 at ZPn. The signals P1OFF, P2OFF, and P3OFF, each generated by a copy of the circuit in Fig. 2, indicate that the current pel of image plane 1, 2, or 3, respectively, is either transparent or outside of the visible window, i.e., blanked. Finally, the signal IP represents the pel stream that goes to the lookup table and DACs to get displayed on the monitor. It is a composite of pel streams 1, 2, and 3, formed by the Plane Selection Control logic described below.

The Priority Registers determine the priority of the image planes. In this implementation, there are three registers, for High, Middle, and Low priority. The image plane number (1, 2, or 3) is placed in a priority register to allow it to participate in the selection process. If an image plane number does not appear in one of the priority registers, it is not used at all and cannot be visible. The use of the priority registers is explained below.

Fig. 2 represents the logic for each image plane that generates the PnOFF signals in Fig. 1. HCNT represents the outpu...