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Shift Register Latch for Delay Testing

IP.com Disclosure Number: IPCOM000036167D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

McAnney, WH: AUTHOR

Abstract

Testing for delay faults requires a pair of patterns, an initialization pattern and a transition pattern. Delay testing in a double-latch LSSD environment, as noted in Section VII of [*], requires that the usual S cycles of A/B shift clocks for a scan string of length S be replaced by S-1 cycles followed by an A clock. This leaves each L1 latch with a value obtained from its predecessor L2, and (obviously) each L2 with the value in its succeeding L1. The L2 values initialize certain paths through the logic. Now pulsing the B clock will shift the L1 value into L2 and hence launch a transition into the logic. This whole process is called 'transition shifting'.

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Shift Register Latch for Delay Testing

Testing for delay faults requires a pair of patterns, an initialization pattern and a transition pattern. Delay testing in a double-latch LSSD environment, as noted in Section VII of [*], requires that the usual S cycles of A/B shift clocks for a scan string of length S be replaced by S-1 cycles followed by an A clock. This leaves each L1 latch with a value obtained from its predecessor L2, and (obviously) each L2 with the value in its succeeding L1. The L2 values initialize certain paths through the logic. Now pulsing the B clock will shift the L1 value into L2 and hence launch a transition into the logic. This whole process is called 'transition shifting'.

Using transition shifting, however, not all of the possible transitions can be obtained [*]. Suppose the delay test requires that 2 adjacent SRLs experience a transition from 1 to 0. Then the 2 L1's should contain 0 and the 2 L2's should contain 1, a pattern obviously impossible to obtain by transition shifting.

It is suggested in [*] that the number of untestable delay faults (untestable because the patterns are not obtainable with transition shifting) may be rather small in practice. For those few faults, it is suggested that the affected SRLs be replaced by the following shift register latch.

The SRL shown in the figure is a standard L1/L2 latch combination with an added L1 system port marked D2 that is clocked by C2. The D2 port is connected to -L2. The Load Transit...