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Hysteresis Receiver With Voltage Regulator

IP.com Disclosure Number: IPCOM000036168D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Feng, ED: AUTHOR [+6]

Abstract

An electrical circuit has been proposed for detecting specific incident driver signal levels with acceptable noise tolerance in a direct access storage device environment.

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Hysteresis Receiver With Voltage Regulator

An electrical circuit has been proposed for detecting specific incident driver signal levels with acceptable noise tolerance in a direct access storage device environment.

A conventional hysteresis receiver circuit (Fig. 1) is designed to receive logic levels of: logical '1' = 2.31 V

logical '0' = 0.49 V

Complementary outputs are compatible with a dual input push-pull driver to provide an inverting or non-inverting function.

When a logical '0' is applied to node IN, a reference voltage is established at the base of T2. This is dependent upon R1, R2, R3 and R4 and the voltage at node VR'. For a rising input transition the threshold is nominally set at 1.6 V. For a falling input transition the nominal threshold is 1.35 V based on the value of resistors R1, R2 and R3 and voltage VR'. The reference voltage of the current switch between T1 and T2 is dynamic depending upon the logical state of the input, thereby providing the hysteresis.

(Image Omitted)

The proposal suggests the design of Fig. 2 which includes a voltage regulator whose details are found in prior art. The switching interval for this configuration for either a rising or falling transition is limited to 270mV. The foregoing is based on automated statistic transient analysis program (ASTAP) results with a temperature from 10-100oC, power supply from 4.5 V-5.5 V, ground shift from - 0.015 V to +0.125 V and chip process variation. The small switching interval permit...