Browse Prior Art Database

Single Hex/Binary Floating Point Unit

IP.com Disclosure Number: IPCOM000036172D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 6 page(s) / 163K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR [+6]

Abstract

This article describes a common hardware design approach to implementing a common hexadecimal floating point (FP) architecture with an IEEE binary FP unit (FPU) as a single hex/binary FPU.

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Single Hex/Binary Floating Point Unit

This article describes a common hardware design approach to implementing a common hexadecimal floating point (FP) architecture with an IEEE binary FP unit (FPU) as a single hex/binary FPU.

The hex FP arithmetic system is mostly a 'subset' of the binary FP arithmetic system. Therefore, this design is based on the premise that beyond the binary FP implementation, a minimum of logic would be necessary for the implementation of hex FP arithmetic. The general approach followed is to provide the basic data path and control structure for an optimized binary FP design, with the 'hooks' required to include hex FP, then add features to fully implement hex.

Fig. 1 illustrates the functional unit organization (Control, FP register (FPR), Exponent, Normalize, Add, Multiply, and Divide). It will be used for referencing how the various operations are supported in the hex/binary design. Similar designs would still have to support the same functions but not necessarily with the same complementary metal-oxide semiconductor (CMOS) technology or logical organization.

(Image Omitted)

Data Formats

To consider the differences between the hex and binary FPUs, first compare the respective data formats which they support:

(Image Omitted)

HEX:

SP - Single Precision format (32 bits) - S, E=7, F=24

bits

DP - Double Precision format (64 bits) - S, E=7, F=56

bits

BINARY:

SP - Single Precision format (32 bits) - S, E=8, F=23

bits

DP - Double Precision format (64 bits) - S, E=11, F=52

bits

DE - Double Extended format (79 bits) - S, E=15, F=63

bits

SI - Short Integer format (32 bits) - 2's Complement

value

LI - Long Integer format (64 bits) - 2's Complement

value

Note: All format fields are left justified.

The FPU utilizes a 67-bit fraction internal chip dataflow (2-34 bit transfers between chips). This supports the above IEEE double- extended format for all

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arithmetic operations, but can also be used to handle all other binary formats as well as hex formats. The FPR chip holds unique sets of 8 hex FPRs and 8 binary FPRs (per this design requirement) which feed common 'unpack' logic for unpacking the fraction from the various formats (see Fig. 2). The FPR provides the operands for all instructions and stores the result in the appropriate hex or binary register.

Some altering of the fraction is required in the ADD chip to support hex single and double-precision arithmetic. This is because as operands are aligned (shifted right) in hex, the bits which are shifted out of the range of precision (past the 4-bit guard digit) must be zeroed out. This is accomplished by masking out these bits at the adder input mux for the aligned operand, before any add/sub/compare operation is performed. All binary arithmetic operations are defined in the DE 67- bit working format and will therefore always maintain valid G,R,S bits used for rounding along with the 64-bit fraction.

The multiply chip does not differentiate between hex an...