Browse Prior Art Database

Using a Portion of the Boundary Register As the Identification Register

IP.com Disclosure Number: IPCOM000036178D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 74K

Publishing Venue

IBM

Related People

Bardell, PH: AUTHOR [+4]

Abstract

In a standard design-for-testability architecture based on the boundary scan methods [*], a device identification (ID) register is included that, on instruction, is loaded with information regarding the component and is then scanned to serially transmit this component information to test equipment or an other external resource. The information is typically the identification of the manufacturer, the com (Image Omitted) ponent part number and engineering change level, and for programmable devices, the device identification. One application of the register is to easily distinguish manufacturers of devices on a mixed technology board (one where multiple component sources are used).

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Using a Portion of the Boundary Register As the Identification Register

In a standard design-for-testability architecture based on the boundary scan methods [*], a device identification (ID) register is included that, on instruction, is loaded with information regarding the component and is then scanned to serially transmit this component information to test equipment or an other external resource. The information is typically the identification of the manufacturer, the com

(Image Omitted)

ponent part number and engineering change level, and for programmable devices, the device identification. One application of the register is to easily distinguish manufacturers of devices on a mixed technology board (one where multiple component sources are used).

A shift register latch (SRL) that is suitable for use as a stage in the device identification register is shown in Fig. 1. The ID Code Bit input is hard-wired to a logical 0 or 1 level depending upon the value needed for the ID at that bit position in the register. The ID Code Bits are loaded into the register by CAPTURE ID CLK, one pulse of which occurs when "Read Identification Register" is the instruction. Following this load, the register is scanned out using the SHIFT A and SHIFT B clocks.

As defined in [*], the device identification register is a separate register within the architecture. However, a portion of the boundary scan register can be used to implement the device identification function, saving almost all the circuitry in the original identification register.

Fig. 2 shows the boundary scan register circuitry for a component primary output pin. (The circuitry for an input pin is nearly identical.) Wh...