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N-Well Bias Regulator Circuit for CMOS Dynamic Memories

IP.com Disclosure Number: IPCOM000036184D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Sakaue, Y: AUTHOR [+2]

Abstract

Disclosed is a circuit for the N-well bias regulation in CMOS dynamic memories. The circuit compensates the base threshold voltage variation of array devices in the N-well by changing the N-well bias.

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N-Well Bias Regulator Circuit for CMOS Dynamic Memories

Disclosed is a circuit for the N-well bias regulation in CMOS dynamic memories. The circuit compensates the base threshold voltage variation of array devices in the N-well by changing the N-well bias.

The threshold voltage of P-channel array device (Vtp) is a function of the base threshold voltage(Vto) which is defined to be at zero back-gate bias voltage and the N-well bias(Vnw). For the array device, the back-gate bias effect allows compensation of the Vto variation to occur, if there is proper tracking between Vnw and Vto. For example, supplying higher Vnw compensates low Vto that leads to low Vtp. It depends on the amount of the Vnw change how effective the compensation is. A N-well bias regulator that has the capability to change Vnw depending on Vto improves reliability of the cells by reducing the Vtp variation. Fig. 1 shows the configuration of such a regulator.

The N-well bias regulator is embodied in a CMOS circuit. The voltage comparator consists of two P-channel devices of the same W/L and a current comparator as shown in Fig. 2. The output of this voltage comparator turns off when the N-well bias rises above (2Vdd - Vref). Vnw is: Vnw = 2Vdd - Vref (1)

The reference voltage generator has an unique structure. In order to have proper tracking between Vnw and Vto, it is designed so that Vref rises for high Vto, and falls for low Vto. The circuit consists of a fixed voltage source (Vs), a source fol...