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Folded Trench Capacitor CMOS Cell

IP.com Disclosure Number: IPCOM000036189D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Arienzo, M: AUTHOR

Abstract

A technique is described whereby an ultra-thin folded trench capacitor CMOS cell is constructed utilizing improved selective epitaxy techniques. Described is a means of fabricating small size CMOS cells, with trench capacitor, that is operational in ultra large-scale integrated (ULSI) circuits.

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Folded Trench Capacitor CMOS Cell

A technique is described whereby an ultra-thin folded trench capacitor CMOS cell is constructed utilizing improved selective epitaxy techniques. Described is a means of fabricating small size CMOS cells, with trench capacitor, that is operational in ultra large-scale integrated (ULSI) circuits.

Typically, the conventional method of producing a trench capacitor for a CMOS cell is to etch silicon, by means of RIE, to form a dielectric in the inside walls of the trench and to refill and planarize the trench. However, the steps required are complicated and the yield is low. Also, the need for smaller chip dimensions requires deeper trenches.

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So as to provide trench capacitors for multi-megabit dynamic random-access memory (DRAM) devices, which require a distinctive reduction in size, the concept utilizes existing processes 1,2, such as the use of selective epitaxy to grow N or P-well functional CMOS circuits. The concept describes a folded trench capacitor (FTC) cell in an N-well; however, a P-well can be similarly obtained by reversing all dopings from p to n and from n to p.

After etching the N-well in p-episilicon and after an optional implant at the bottom of the well, the capacitor dielectric is grown, or deposited, and the surface of the silicon is protected by an oxide/nitride mask. The trench contacts are opened on the top surface, as shown in Fig. 1, by RIE, or alternatively on the well sidewalls. Conformal in-situ doped polysilicon is now deposited forming the trench plate and contacts the silicon where the contacts were opened. A doped conformal polysilicon film is now available 3. A second dielectric is then deposited on top of the doped polysilicon. Alternatively, this second dielectric may be deposited after the next trench definition step, thereby guaranteeing the well isolation at the well corners in event multiple trenches are required in one well.

Next, a photoresist masking step is implemented to define the trench shape, as shown in Fig. 2....