Browse Prior Art Database

Means for Reducing Collisions in a Multiprocessor Interconnection Network

IP.com Disclosure Number: IPCOM000036193D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Robinson, JT: AUTHOR [+2]

Abstract

A multiprocessor system normally contains an interconnection network that connects processors to memories or connects processors among themselves. The sorting mechanism described here is used to order requests at an input to an interconnection network in a manner that tends to reduce collisions within the network at the receiver nodes at the network outputs. This tends to improve the utilization of the network.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Means for Reducing Collisions in a Multiprocessor Interconnection Network

A multiprocessor system normally contains an interconnection network that connects processors to memories or connects processors among themselves. The sorting mechanism described here is used to order requests at an input to an interconnection network in a manner that tends to reduce collisions within the network at the receiver nodes at the network outputs. This tends to improve the utilization of the network.

The purpose of the mechanism is to reduce contention by ordering requests for minimum contention when ordering is possible. Fig. 1 shows a multiprocessor system with an interconnection network that connects N processors to N memories. Fig. 2 shows the same system augmented by the access mechanism, which consists of a collection of buffers, one per processor, that orders pending requests at the input of the network.

The buffer tries to issue requests so that outstanding requests from all processors are issued in the same order, which is generally in ascending order by memory module index. The accesses are phased with respect to each other so that at any given clock cycle, each processor favors access to a different memory.

(Image Omitted)

The objective is to issue the requests from each processor in the same order. While this tends to reduce collisions, but not eliminate them, if a collision should occur, subsequent references tend to become phased with respect to each other, which tends to reduce contention in the future. The method described below works best when all processors are executing code from the same porti...