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Self-Checking Pair Swapping Mechanism

IP.com Disclosure Number: IPCOM000036201D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Truong, KT: AUTHOR

Abstract

Self-Checking Pair is a practical fault tolerant concept which provides near 100% hardware error detection capability besides providing a "hot- spare" to replace the failing part. The processor pair, with one being the 'active' processor and the other being a 'checker' processor is called a self-checking pair. The swapping process is a role reversal that could lead to both processors being 'active.' This article sets forth a technique that detects errors and prevents the undesirable consequence of a pair of processors running in 'lock-step' while participating in a swapping process. The method to avoid this problem employs a so-called 'pseudo latch' as a communication device to serialize the swapping action into 'command, response and activate' protocol.

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Self-Checking Pair Swapping Mechanism

Self-Checking Pair is a practical fault tolerant concept which provides near 100% hardware error detection capability besides providing a "hot- spare" to replace the failing part. The processor pair, with one being the 'active' processor and the other being a 'checker' processor is called a self-checking pair. The swapping process is a role reversal that could lead to both processors being 'active.' This article sets forth a technique that detects errors and prevents the undesirable consequence of a pair of processors running in 'lock-step' while participating in a swapping process. The method to avoid this problem employs a so-called 'pseudo latch' as a communication device to serialize the swapping action into 'command, response and activate' protocol.

Fig. 1 illustrates the 'pseudo latch' concept. A single wire connects to the processor pair with a transreceiver at each end. Its receiver output is inverted and selected by the 'active' signal for controlling its driver output. The driver output is also controlled by a swapping command signal. This interlock mechanism allows the 'checker' to initiate the command that forces the 'active' processor to hold its 'pseudo latch' low. The combination of the transreceiver and the inverter forms the so-called 'pseudo latch' to register a command. A response made on the same wire can prevent any 'stuck-at error' from causing the processor pair to be 'active' at the same time.

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