Browse Prior Art Database

Improved Polishing Techniques for Silicon Wafers

IP.com Disclosure Number: IPCOM000036204D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 81K

Publishing Venue

IBM

Related People

Esslinger, DC: AUTHOR [+2]

Abstract

A technique is described whereby polishing of dielectric films, during the fabrication of silicon chips, is improved so as not to destroy device structures on the wafers. The concept implements polishing procedures so that small device lands, in a field material, can be maintained intact without undue attack of the field material. (Image Omitted)

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Improved Polishing Techniques for Silicon Wafers

A technique is described whereby polishing of dielectric films, during the fabrication of silicon chips, is improved so as not to destroy device structures on the wafers. The concept implements polishing procedures so that small device lands, in a field material, can be maintained intact without undue attack of the field material.

(Image Omitted)

Typically, chemical-mechanical polishing is used to finish the surface of silicon wafers prior to the start of device processing. Slurries are used that controllably polish the wafer surface while chemically attacking that surface simultaneously. However, polishing has rarely been used during device processing due to the non-uniformities involved.

However, polishing can be extended to device processing through the use of selective slurry materials that polish silicon rapidly, without polishing SiO2 or Si3N4 appreciably. For example, this polishing extension allows the polisher to be used for the etch back of silicon after the deep isolation trench has been filled. As such, the polishing process stops on a nitride surface which covers all areas except the deep trench, as shown in Fig. 1.

However, when it is desired to polish down to small lands in a field of material that is polished rapidly, the polishing has proved to be more difficult. In this case, the small area of the barrier material does not withstand the polishing even when the slurry is designed to be selective. In particular, when the film being polished is polysilicon, and the polish must stop on silicon nitride over a small silicon land (the device area), the polish attacks the edges of the exposed lands.

(Image Omitted)

This results in two detrimental effects: a) the loss of integrity of the device area, and b) the thinning of the polysilicon designed to be a conductor, as shown in Fig. 2.

The concept described herein provides a means of overcoming both of the detrimental effects by taking advantage of an observed polishing effect on the topology when using selective slurry. Polished wafers, with topology, have shown that a raised land of silicon nitride, or silicon dioxide, polishes even in selective slurry while a flat surface of the same material does not, as shown in...