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Browse Prior Art Database

Shared Memory Arbiter Circuit

IP.com Disclosure Number: IPCOM000036213D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Frey, DE: AUTHOR [+2]

Abstract

An inexpensive arbiter circuit permits either a printer communication adapter or microprocessor to communicate with shared random-access memory (RAM) on a first come-first-served basis, but limits the access of each to one memory cycle if the other is waiting, and prevents bus contention or race conditions. (Image Omitted)

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Shared Memory Arbiter Circuit

An inexpensive arbiter circuit permits either a printer communication adapter or microprocessor to communicate with shared random-access memory (RAM) on a first come-first-served basis, but limits the access of each to one memory cycle if the other is waiting, and prevents bus contention or race conditions.

(Image Omitted)

The arbiter logic diagram is illustrated in Fig. 1, and Figs. 2 and 3 show the signal timing relationships for adapter RAM access and microprocessor RAM access, respectively. The communication adapter activates -FE RAM Request signal and is gated onto the RAM bus by -Gate uP to RAM. The -Chip Sel and - OE signals are RAM control lines, and adapter clocks are -B, -C and the microprocessor clock is the uP clock. Other signals, -C Time, -B Time, -Clock 1 and +Clock 2, are generated with the same clocking network.

When the adapter generates -FE RAM Request and -Gate uP to RAM is already active, the adapter request is blocked by gate G1. If the adapter request is not blocked, then the input to flip-flop T1 is set and, on the next -ClK 1/-C Time at gate G2, -FE RAM Grant becomes active. The input to shift register SR goes high and, on the next fall

(Image Omitted)

ing edge of uP clock, -Chip Sel is active at gate G6. Signal -OE from gate G9 is generated from the adapter. The adapter RAM cycle ends after two uP clock pulses when output A of shift register SR goes low to degate -Chip Sel and -FE RAM Grant becomes inactive on the next rising edge of +Cl...