Browse Prior Art Database

High-Speed ECL Circuit

IP.com Disclosure Number: IPCOM000036214D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 7 page(s) / 157K

Publishing Venue

IBM

Related People

Chuang, CK: AUTHOR [+2]

Abstract

A technique is described whereby the power/speed performance of ECL circuitry is improved by reducing the DC power dissipation in the circuits by implementing a low-power AC-coupled active pull-down emitter follower output stage.

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High-Speed ECL Circuit

A technique is described whereby the power/speed performance of ECL circuitry is improved by reducing the DC power dissipation in the circuits by implementing a low-power AC-coupled active pull-down emitter follower output stage.

In conventional ECL circuitry, the emitter follower output stage typically dissipates approximately 45% of the total gate power (with one-phase output). This ratio increases to 60% in low-power operation. It has been determined that by eliminating, or substantially reducing the steady-state power in the emitter follower, the switching speed can significantly be enhanced. This is because the switching current can be increased in the differential pair, while maintaining lower, or the same power, dissipation at each gate. This approach is particularly advantageous in high-speed, low-power operation where power dissipation in the output stage is a problem. Therefore, the concept described herein presents several ECL circuits, using AC-coupled pull-down techniques at the emitter follower stage, to achieve high-speed and low power operation.

(Image Omitted)

The conceptual representation of a high-speed ECL gate with a low power output stage is shown in Fig. 1. SW1 is an electronic switch and is used so as to be activated briefly during the output high-to-low transition. This is so that the output node can be discharged quickly, near or below, the output low voltage level VOL . In the latter case, Q3 will be turned on strongly for a short period of time so as to charge the output node back to VOL. This charge-back action is fast due to the emitter follower operation. The undershoot is at most a few hundreds of a mV below VOL, being limited by the forward base-emitter junction of Q3.

The high-to-low transition time is determined by the discharge through SW1, which can be faster than the conventional ECL circuit and with lower DC power dissipation. A low steady-state current IO is maintained after the transition and is necessary for switching noise considerations. Its value may be tailored for specific applications and is typically held below 100 mA. The output low-to-high operation is similar to the fast charge-back operation, except that the final output voltage is now VOH .

(Image Omitted)

The emitter follower is efficiently utilized in this application since it conducts high current only during a switching transient. A secondary advantage stems from the fact that the steady state current through Q3 is low and therefore VOH is approximately 100 mV closer to VCC than in the conventional ECL circuit. Therefore, a lower VCC may be used, further reducing the power dissipation in the gate. In addition, the lower end of SW1 may be returned to VEE without increasing the power dissipation significantly, thereby eliminating the need for an intermediate supply voltage VM . SW1 is considered to be the key to this concept and can be implemented most effectively by AC-coupling a low- to-high switching...