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Active Terminators for CMOS Drivers

IP.com Disclosure Number: IPCOM000036220D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Pricer, DW: AUTHOR

Abstract

A method is shown for substituting active transistors for terminating resistors on CMOS-driven transmission lines to provide substantial benefits in data transmission rates, power dissipation, overshoot protection, and rapid dampening of transients on the lines.

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Active Terminators for CMOS Drivers

A method is shown for substituting active transistors for terminating resistors on CMOS-driven transmission lines to provide substantial benefits in data transmission rates, power dissipation, overshoot protection, and rapid dampening of transients on the lines.

By terminating data transmission lines in their characteristic impedance, rapid communications over long lines is facilitated. In instances where such lines are driven at their midpoint, characteristic impedance terminators at both ends of the line are utilized. The "quieting" of the line after data transmission is hastened because any transients reaching the extremities of the line are perfectly terminated which results in no reflected energy. These solutions proved effective for emitter coupled logic (ECL) circuit technology due to the small signal swings and superior current handling capabilities. When higher levels of integration in the CMOS technology emerged, the levels of simultaneous I/O switching increased. Also, with wider signal voltage swings, an increase in power dissipation and power transients resulted. By terminating CMOS-driven long lines with an active terminator circuit, higher transmission rates and other transmission line performance attributes can be achieved.

Referring to Fig. 1, a simple FET inverter circuit is shown which can be used as a transmission line terminator. When the transistors are matched for equal transconductance, the inverter accurately simulates a linear resistor over most of the operating range and quiescent power dissipation is greatly reduced compared with a two resistor equivalent. Termination impedance values of interest (30 - 50 ohms) can be constructed from moderate size transistors. Typically 100:1 to 200:1 W/L ratios. Fig. 2 shows the inverter circuit terminator used with four additional transistors (shown as switches) which may be activated on command. In a bus-organized system where multiple drive and receive points exist, the most advantageous position for the termination impedance may change from moment to moment, depending on the physical location of the drive and receive points. Since addresses normally precede data on a bus, the direction of traffic is known in advance, allowing the system to judiciously activate and de- activate terminator circuits.

As shown in Fig. 3, the input impedance of a simple CMOS inverter wired short circuit common drain to common gate can be constructed graphically. For a given input voltage, the input current is the su...