Browse Prior Art Database

Delay Unit

IP.com Disclosure Number: IPCOM000036227D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Katayama, Y: AUTHOR [+2]

Abstract

Disclosed is a fuse adjustable CMOS delay circuit. The circuit can delay the signal when fuse is blown with minimum DC power dissipation. The rising and falling edge can be adjusted separately.

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Delay Unit

Disclosed is a fuse adjustable CMOS delay circuit. The circuit can delay the signal when fuse is blown with minimum DC power dissipation. The rising and falling edge can be adjusted separately.

The key block of the invented delay chain is shown in Fig. 1. There is no limitation for the number of pairs of inverters between node A and B, but an even number of inverters must be used. Before the fuse is blown, T1 has nothing to do with the circuit behavior because both source and drain are grounded. Thus, this circuit works as a two inverter delay chain. When the fuse is blown, only the falling edge of the pulse at node C is delayed because of the stacked NMOS transistors T1 and T2. The soft latch T4 is used to keep node C at 5 V. During

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the delay time, T4 will keep node C high in spite of the charge sharing between the node C and D in this floating period when only T2 is on (T1 is off). The amount of delay can easily be adjusted by changing the number of inverter stages or changing W/L in each inverter.

This circuit block can be arranged as is shown in Fig. 2 to make possible 3 different delay timing selections for both rising and falling edges of the input pulse. The delay block is stacked for both the rising edge and falling edge to achieve 2, 6, and 10 inverter delays. Therefore, 3 different delays are provided by a circuit with two fuses. Another alternative of the delay circuit is shown in Fig. 3, which can delay either the rising or...