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Improved Off-Chip-Driver Sequencer for LSSD Testing

IP.com Disclosure Number: IPCOM000036234D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

A circuit is shown which utilizes additional FET switches and low resistance wiring to create a fast shut-off control signal for LSSD testing of semiconductor circuits resulting in improved test time.

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Improved Off-Chip-Driver Sequencer for LSSD Testing

A circuit is shown which utilizes additional FET switches and low resistance wiring to create a fast shut-off control signal for LSSD testing of semiconductor circuits resulting in improved test time.

A current off-chip-driver (OCD) sequencer (DI line) has symmetric turn-on and turn-off lines, resulting in excessive "dead time" during test. Fig. 1 schematically depicts the current DI line layout on a chip. Non-inverting buffers (B1 through B4) delay signal propagation along two sides of the chip due to polysilicon wiring resistance (R1...R4), and further delays are encountered due to an RC time constant related to input capacitances of drivers D1...D4. When the DI line is activated, drivers D1...D4 turn on sequentially, eliminating any potential for simultaneous switching problems. The timing sequence used during LSSD testing is shown in Fig. 2. After internal switching activity stimulated by "A" and "B" clocks stops, the Di line is activated. After the DI signal has propagated to the last OCD, outputs are sampled and the DI line is turned off. When the inactive state of DI line has propagated to the last OCD, a new tester cycle can begin. A technique is shown for eliminating the DI turn-off delay and enhance LSSD test time.

Through the addition of FET switches and utilization of metal signal lines, "dead time" is eliminated by enhancing the DI line turn- off characteristics. Fig. 3 schematically depicts the cha...