Browse Prior Art Database

Bicmos Technology Using Selective Epitaxy

IP.com Disclosure Number: IPCOM000036236D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

A unique process sequence is outlined that uses selective epitaxy to define the region where a high performance bipolar device can be formed in a base CMOS technology.

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Bicmos Technology Using Selective Epitaxy

A unique process sequence is outlined that uses selective epitaxy to define the region where a high performance bipolar device can be formed in a base CMOS technology.

In order to provide a high performance bipolar device in a base CMOS technology, three additional masking steps are utilized, namely, shallow trench isolation, a twin well and dual polysilicon for the gate electrode, which are features of the base CMOS technology.

The additional processing steps that are needed to fabricate an npn bipolar transistor are introduced after the shallow trench isolation is filled with oxide and planarized, and the n-well is implanted. A blocking mask defines a region where silicon is removed to a depth of approximately 0.5 mm. The same mask is used to implant a n+ buried layer, as shown in Fig. 1. An n-type epitaxial layer is then grown selectively in the regions where silicon was removed, using the oxide to block the epitaxial growth in other regions.

A boron field and punch-through tailor implant are used to define the base of the npn device. An additional mask is used to define and implant the n+ reach- through collector contacts. After gate oxide growth, a mask is used to remove the thin oxide from the emitter area. The remaining process steps follow the same sequence as in the base CMOS technology. The n+ polysilicon gate forms the n+ emitter contact while the NMOS and PMOS source/drain and silicide form the collector and b...