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Performance Self-Test for High Performance Random-Access Memories

IP.com Disclosure Number: IPCOM000036240D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Beilstein, KE: AUTHOR [+3]

Abstract

This article relates to accurate performance testing of high performance random-access memories (SRAM and also DRAM used in static column mode) while minimizing tester accuracy requirements.

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Performance Self-Test for High Performance Random-Access Memories

This article relates to accurate performance testing of high performance random-access memories (SRAM and also DRAM used in static column mode) while minimizing tester accuracy requirements.

Tester accuracy is usually +/- 1 nsec. Therefore, with a slow access limit of 80 nsec, the tester is set at 79 nsec. Product may then be tested at 78 nsec to guarantee the 80 nsec performance. Cutting into the distribution of an 80 nsec product by 2 nsec will not create a major yield problem; however, a SRAM of 10 nsec access limit or a DRAM in static column mode with an access limit of 10 nsec will result in a significant yield impact by cutting into the performance distribution by 2 nsec.

By setting the device under test (DUT) with a data pattern that sequentially provides the next address, and letting the DUT provide its next input, a highly accurate performance measurement can be made since the device runs as a ring oscillator. The lowest output would measure the highest frequency and each succeeding output measures a frequency of 1/2 the previous one. To provide this capability, a number of additional circuits are required. When a chip has a number of data outputs (Y) greater than the number of address inputs (X), then the added circuitry is one AND on the chip enable input for a SRAM, or on the column address enable (CAS) line for a DRAM, and Y X/2 binary counter positions and Y X/2 way ANDs. When the chip has a number of data outputs (Y) less than the number of address inputs (X), then X - Y binary counter positions and X - Y 2-way ANDs are added to cycle all input addresses.

Referring to the figure,...