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Browse Prior Art Database

Digital Timing Generator

IP.com Disclosure Number: IPCOM000036242D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

King, C: AUTHOR

Abstract

A high performance memory which is clocked at a fixed rate is the basis of a timing generator having programmable digital cycle time and programmable pulses within a cycle. There is no dead time associated with this generator, i.e., a pulse can be programmed to occur at any time within a given cycle. This high performance timing generator has application in digital test equipment, for instance.

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Digital Timing Generator

A high performance memory which is clocked at a fixed rate is the basis of a timing generator having programmable digital cycle time and programmable pulses within a cycle. There is no dead time associated with this generator, i.e., a pulse can be programmed to occur at any time within a given cycle. This high performance timing generator has application in digital test equipment, for instance.

The concept of creating a timing generator based upon a high performance memory clocked at a fixed rate is block diagrammed in Fig. 1. A single bit programmed as a "1" in the first four bits of a word in high performance memory 2 defines the timing of a leading edge of a pulse and a single bit of the next four bits of the same word programmed as a "1" defines the timing position of the trailing edge of that pulse. When memory 2 has a 40 ns cycle time, and a 10 ns select rate is applied to multiplexers 4 and 6, each memory bit corresponds to a 10 ns time slice. Programmable 1 ns delays 8 and 10 provide 1 ns resolution. A flip-flop (latch) 12 is set or reset by pulses on input lines S or R, thus providing a pulse on output line OUT having specified (programmed) leading and trailing edge positions within a memory cycle time.

Fig. 2 is a block diagram showing the use of primary memory 2 (as in Fig. 1) and a second, or branch, memory 2B having a faster access time, e.g. 10 ns, to allow the beginning of a new cycle without any time loss (dead time). Via...