Browse Prior Art Database

Priority Sorting in a Message Acceptance Mechanism

IP.com Disclosure Number: IPCOM000036243D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 113K

Publishing Venue

IBM

Related People

Baird, DP: AUTHOR [+3]

Abstract

This article describes using a common message buffer area in a computer I/O subsystem in a scheme where message routing and prioritization are based on both the message itself and on the configuration of the hardware.

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Priority Sorting in a Message Acceptance Mechanism

This article describes using a common message buffer area in a computer I/O subsystem in a scheme where message routing and prioritization are based on both the message itself and on the configuration of the hardware.

In some existing message acceptance mechanisms for an I/O subsystem, all messages are placed in a common buffer which must be scanned by software to find the highest priority item. A single message increases (or degrades) response time for high priority messages compared to systems with priority interrupt mechanisms in hardware.

The scheme disclosed herein improves response time by sorting the messages into 2**n prioritized buffers as the messages arrive. The buffer is selected by the message priority value (MPV) field in each message. The MPV field is in effect the message priority for both hardware and software.

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Rather than having a single message buffer offset register that specifies both the address base for the message buffer area and the offset counter, there is a separate message buffer base register (MBBR) and multiple message buffer offset registers (MBORs). A message acceptance control register (MACR) can be provided that permits programmed control of the number of MBORs to be used.

Fig. 1 shows the relationship between the message buffer area defined by the MBBR and the use of the area as controlled by a set of MBORs. Fig. 2 shows the MACR that is described in this article and the source of the bits to form the storage address used when storing a message.

The MBBR specifies the start of an area of contiguous storage that is allocated as buffer pairs where there can be a buffer pair for each MBOR that is implemented. The size of the buffers is determined by the size of the offset counters in the MBORs. The number of buffer pairs that are used ay any point in time is controlled by the MACR.

Each MBOR consists of a latch (s) that indicates which one of the pair of buffers is to be used and an offset counter. The MPV is used to select the MBOR to be used in storing that message and in asserting the appropriate I/O interrupt t...