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Process for Making Asymmetric Field-Effect Transistors

IP.com Disclosure Number: IPCOM000036254D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Nowak, EJ: AUTHOR [+2]

Abstract

Different doping in source and drain of field-effect transistors (FETs) is accomplished by means of angular blanket exposure of a photoresist shadowed by polysilicon lines. Development of positive photoresist made soluble by exposure leaves no resist in contact areas completely exposed and a wedge-shaped resist coating remains in a contact shadowed by a polysilicon line edge, e.g., a gate conductor. Ion implantation then creates a steep doping profile in source junctions while a graded doping profile is formed in drain junctions.

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Process for Making Asymmetric Field-Effect Transistors

Different doping in source and drain of field-effect transistors (FETs) is accomplished by means of angular blanket exposure of a photoresist shadowed by polysilicon lines. Development of positive photoresist made soluble by exposure leaves no resist in contact areas completely exposed and a wedge- shaped resist coating remains in a contact shadowed by a polysilicon line edge, e.g., a gate conductor. Ion implantation then creates a steep doping profile in source junctions while a graded doping profile is formed in drain junctions.

Referring to Fig. 1, standard processing is used to form recessed oxide (ROX) region 2 on the drain contact edge and ROX 4 on a source contact edge in silicon substrate 6. Gate conductor 8 is also formed by standard processing over gate insulator 10. Then, a positive photoresist (PR) is applied, dried, and exposed to light coming in at an angle A to the substrate surface. After development, a wedge-shaped region of PR 12 remains over a portion of the drain contact region. When ion implantation normal to the substrate surface is performed, a graded doping profile 14 is formed in the drain contact while and abrupt profile 16 is formed in the source contact area. Normal processing is used to complete the device after PR 12 is removed.

Block masking is used to restrict ion implantation to areas of a circuit having devices with drains all on the same side of gate conductors. A new coat o...