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Approach for Fast Interrupt Response in Processors Using Pipeline Architectures

IP.com Disclosure Number: IPCOM000036255D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Jones, GD: AUTHOR

Abstract

An approach is described for improving the interrupt response of signal processors that use pipelined architectures. This is done by using an interrupt state register in the data flow that makes all instruction sequences transparent to interruption. This register, plus a special restore instruction for its control, allows the architecture to avoid the current practice of using interrupt protection on instruction se (Image Omitted) quences. By eliminating protected strings of instructions, the interrupt response is made deterministic, being independent of the program flow, and the minimum interrupt latency is achieved. The approach will be described for a processor having a three-phase pipeline segmented as (INSTRUCTION FETCH), (DECODE/BRANCH) and (EXECUTE).

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Approach for Fast Interrupt Response in Processors Using Pipeline Architectures

An approach is described for improving the interrupt response of signal processors that use pipelined architectures. This is done by using an interrupt state register in the data flow that makes all instruction sequences transparent to interruption. This register, plus a special restore instruction for its control, allows the architecture to avoid the current practice of using interrupt protection on instruction se

(Image Omitted)

quences. By eliminating protected strings of instructions, the interrupt response is made deterministic, being independent of the program flow, and the minimum interrupt latency is achieved. The approach will be described for a processor having a three-phase pipeline segmented as (INSTRUCTION FETCH), (DECODE/BRANCH) and (EXECUTE). It is assumed that branch instructions are executed on phase 2 and have no compute action on phase 3.

The pipeline-related state parameters that must be saved at the onset of an interrupt and be reestablished after interrupt servicing are: 1. ALU conditions, 2. contents of the data bus, and 3. the branch to-be-taken address.

Other operands which define the state of the program being executed, such as the contents of ALU register, accumulators, etc., are saved and restored by other, conventional techniques.

Operation of the Interrupt State Register (ISR) is based on the realization that when an interrupt occurs there is pertinent state information either at the end of phase 2 of the pipeline execution or at the end of phase 3 but not both. Since ALU conditions are normally set in a status register, a single additional register is all that is necessary to completely describe the state of the interrupt instruction, regardless of its type. The use of the Interrupt State Register (ISR) in preserving the pipeline parameters is summarized below:
1. If a branch is to be taken at the end of phase 2 of the instruction interrupted, a branch pending (BP) bit is set in the status register and the branch target

address is loaded into the interrupt state register

(ISR). The interrupt is then serviced. BP is set for

direct and indirect branches and for conditional

branches that are taken.
2. If a branch is not to be taken at the end of phase 2 of the instruction interrupted, the contents on the Common Data Bus are loaded into ISR at the end of phase 3.

The interrupt is serviced at the end of phase 2. BP is

not set.

These actions combined with the normal procedure of storing ALU conditions in the status register at the end of phase 3 insure that all pertinent pipeline state

1

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information is saved when the interrupt occurs. Fig. 1 illustrates operation of the ISR when an interrupt occurs.

The pipeline state parameters...