Browse Prior Art Database

Simulation Model for Optical Delay

IP.com Disclosure Number: IPCOM000036262D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Fogg, RG: AUTHOR [+5]

Abstract

Disclosed is a behavioral to simulate the fiber link in an optical data path. It provides programmable delays so that all the various data and control paths in the hardware can be verified.

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Simulation Model for Optical Delay

Disclosed is a behavioral to simulate the fiber link in an optical data path. It provides programmable delays so that all the various data and control paths in the hardware can be verified.

The processor complex uses a fiber-optic connection to other processors and components. The link hardware is responsible for obtaining serial information from the fiber-optic link and transferring it to the processor main storage. To test this logic, two sets of hardware are used to communicate with each other with a behavioral in between to simulate the link.

To fully test the many different protocols defined by the serial architecture and different delays associated with the asynchronous communication over the link, the behavioral had to be designed to generate any arbitrary delay between when it received data from one channel and transmitted it to the other. For maximum flexibility this delay was designed to be programmable from within the test case instead of from outside the simulation.

The behavioral is basically a first-in, first-out (FIFO) buffer. It puts input data into the FIFO buffer and takes it out of this buffer to send to the output. In a no- delay situation the depth of this buffer is equal to the header size of the serial data on the link. The behavioral monitors the input data stream for a start of the frame field. One of the fields in the header is used to specify the delay parameter. The output of the behavioral is delayed...