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Instruction Buffer to Support Multiple Fetches and Dispatches

IP.com Disclosure Number: IPCOM000036273D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Grohoski, GF: AUTHOR [+2]

Abstract

When many instructions are being considered for dispatching in an instruction unit, a buffering scheme which allows timely and efficient instruction access is required. The instruction buffer must simultaneously provide instructions to the decode and dispatch logic and also receive instructions from the instruction fetching unit.

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Instruction Buffer to Support Multiple Fetches and Dispatches

When many instructions are being considered for dispatching in an instruction unit, a buffering scheme which allows timely and efficient instruction access is required. The instruction buffer must simultaneously provide instructions to the decode and dispatch logic and also receive instructions from the instruction fetching unit.

The instruction buffering scheme described here requires less area and time than other buffering schemes considered for this application. A previous implementation required 16 buffers and 10 multiplexers to implement 2 logically equivalent instruction buffers each maintained as a circular queue. This implementation requires only 12 buffers and 5 multiplexers to achieve nearly the same, and in some cases, superior performance. Additionally, the time to access instructions from this buffer scheme is less than the previous scheme.

The instruction buffer consists of 2 logically separate buffers. The sequential buffer contains 8 queue positions. The target buffer contains only 4 queue positions. Each position can hold one instruction. Instructions are dispatched from the sequential buffer. The target buffer is used to hold instructions from prefetched branch targets. Unlike the previous scheme, the sequential and target buffers are "hardwired" and the target buffer can contain only 4 instructions. Thus fewer instructions can be prefetched from branch targets, but in practice this does not measurably affect performance.

The sequential buffer is split into four "columns". Each column has 2 entries. One column receives instructions from one port of the instruction-fetching mechanism. Column 0 contains buffers S0 and S4, column 1 contains S1 and S5, column 2 contains S2 and S6, and column 3 contains buffers S3 and S7.

The target buffer is split into 4 columns, but each column contains only one entry. Column 0 contains T0, column 1 contains T1, column 2 contains T2, and column 3 contains T3.

Each buffer has 2 pointers associated with it. The outcount is a 2-bit pointer which specifies the column containing the oldest instruction in the buffer. Scanning instructions for dispatch starts at the outcount and c...