Browse Prior Art Database

Cache Comparator Structure Using Write-Over Array

IP.com Disclosure Number: IPCOM000036278D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Grohoski, G: AUTHOR [+2]

Abstract

This disclosure describes an efficient cache comparator structure for a computing system which has virtual memory and uses caches to improve performance. This method of efficient comparison works for instruction caches, data caches, or combined instruction/data caches. The method will be described for a 2-way set associative instruction cache, and a 2-way set associative TLB (Translation Look-aside Buffer), but this method works with any combination of set-associativity for the cache and its TLB.

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Cache Comparator Structure Using Write-Over Array

This disclosure describes an efficient cache comparator structure for a computing system which has virtual memory and uses caches to improve performance. This method of efficient comparison works for instruction caches, data caches, or combined instruction/data caches. The method will be described for a 2-way set associative instruction cache, and a 2-way set associative TLB (Translation Look-aside Buffer), but this method works with any combination of set-associativity for the cache and its TLB.

The figure depicts a typical cache directory configuration. Since most modern computing systems have virtual memory, addresses generated by the processor can be either "real" (virtual address translation disabled) or "virtual" (virtual address translation enabled).

When an address is generated by the processor, either for an instruction fetch or for a data access, the address must be compared with the current contents of the cache directory in order to determine if the instruction or data can be fetched from the cache. If a miss occurs, the instruction or data must be fetched from main memory.

As illustrated in the figure, this comparison has 2 modes of operation. In real mode, appropriate bits of the processor address (in register IFAR) are compared with the contents of directory set A and set B using comparators AR and BR, respectively.

In virtual mode, the address in the IFAR first undergoes translation by extending the address to a virtual address, then looking for the virtual-to-real translation in the TLB. Comparators TLBA and TLBB determine if the requested virtual address translation exists in the TLB. If it does, then the real address read from TLB set A or B, as appropriate, is compared with directory sets A an...